Exemplary embodiments of the present invention relate to a semiconductor memory device, and more particularly, to technology for improving a data compression test of a semiconductor memory device.
As a semiconductor memory device is highly integrated with the development of processing technologies, in order to guarantee the reliability of a chip, a test is performed after fabrication for a lengthy time using costly testing equipment.
In semiconductor memory device testing technology, while it is important to reliably perform a test, several tens of millions of cells should be tested at a high speed. In particular, the shortening of a development period of a semiconductor memory device and of a testing time of the semiconductor memory device till placement of an end product on the market directly influences the manufacturing cost of the semiconductor memory device. Therefore, the shortening of the testing time is regarded as critical in terms of productivity and competition among manufacturers.
In general, in the field of a semiconductor memory device, after a memory chip is fabricated, it is necessary to judge a cell as pass or fail. If cells are tested one by one, it takes a long time to test a highly integrated memory device, and costs incurred increase.
Therefore, in an effort to shorten a testing time, a data compression test (also called a parallel test) is performed.
In the data compression test, after the same data are written in a plurality of cells, an exclusive OR gate or the like is used upon read. Therefore, if the same data are read out from the plurality of cells, judgment is made as pass by outputting ‘1’, and, if even one of the data is different from the other data, judgment is made as fail by outputting ‘0’.
FIG. 1 is a view illustrating parts associated with a data compression test of a conventional semiconductor memory device.
A plurality of data transmission lines GIO represent lines which transmit the data read out from a cell array, to the vicinity of output pads. Usually, these lines are called global input/output lines (GIO).
Each of a plurality of data compression circuits COMP receives data from at least two data transmission lines GIO, compresses received data, and outputs compressed data. Data are compressed at a data compression rate, such as of 2:1, 4:1, and so on, depending upon the number of data transmission lines GIO each data compression circuit COMP receives data through. Here, the data compression generates a result, representing whether all the data received by the data compression circuit COMP are the same or even one of the data is different from the other data. For example, if all the data received by the data compression circuit COMP have the same value, an output COMP_OUT of the data compression circuit COMP becomes ‘1’, and, if even one of the data received by the data compression circuit COMP has a different value, the output COMP_OUT of the data compression circuit COMP becomes ‘0’.
A plurality of parallel-to-serial conversion sections P2S receive the compression results COMP_OUT outputted from data compression circuits COMP, parallel-to-serial convert the compression results COMP_OUT at a rate of N:1, and output converted results. The value of N changes depending upon the number of compression results COMP_OUT that each of the parallel-to-serial conversion sections P2S receives. For example, if the parallel-to-serial conversion section P2S receives eight compression results COMP_OUT, as shown in FIG. 1, the parallel-to-serial conversion section P2S aligns in series the compression results COMP_OUT outputted from eight data compression circuits COMP on one line and outputs the serially aligned compression results. Examples of the parallel-to-serial conversion sections P2S include pipe latches.
A plurality of output circuits DQ UNIT output the serially aligned compression results COMP_OUT_S outputted from the parallel-to-serial conversion sections P2S, to an outside of a chip. As illustrated in FIG. 1, the compressed data are outputted to four data pads DQ<0> to DQ<3>. The number of data pads DQ to be used in a data compression test can be changed as desired, depending upon a data compression rate.
While the data compression test is necessary for improving the test efficiency of a semiconductor memory device, in order to perform the data compression test, additional circuits are needed in the semiconductor memory device.
If the area occupied by the additional circuits can be reduced, the productivity of the semiconductor memory device will of course be significantly improved.